# ==============================================================================
#
# Copyright (C) 2022 Sophgo Technologies Inc.  All rights reserved.
#
# TPU-MLIR is licensed under the 2-Clause BSD License except for the
# third-party components.
#
# ==============================================================================

tiu_reg_def = (
    ("cmd_en", 1),
    ("cmd_end", 2),
    ("cmd_id_en", 3),
    ("cmd_id_tpu", 19),
    ("cmd_id_gdma", 35),
    ("cmd_keep", 36),
    ("cmd_intr_en", 37),
    ("tsk_typ", 41),
    ("tsk_eu_typ", 46),
    ("tsk_opd_num", 48),
    ("opt_right_shift", 53),
    ("opt_left_shift", 58),
    ("opt_shift_typ", 59),
    ("opt_res_add", 60),
    ("opt_relu", 61),
    ("opt_left_tran", 62),
    ("opt_winograd", 63),
    ("opt_kernel_rotate", 64),
    ("opt_opd0_sign", 65),
    ("opt_opd1_sign", 66),
    ("opt_opd2_sign", 67),
    ("opt_res0_prec", 70),
    ("opt_opd0_prec", 73),
    ("opt_opd1_prec", 76),
    ("opt_opd2_prec", 79),
    ("opt_opd0_const", 80),
    ("opt_opd1_const", 81),
    ("opt_opd2_const", 82),
    ("short_res0_str", 85),
    ("short_opd0_str", 88),
    ("short_opd1_str", 91),
    ("short_opd2_str", 94),
    ("opd0_x_ins0", 98),
    ("opd0_y_ins0", 102),
    ("opd1_x_ins0", 106),
    ("opd1_y_ins0", 110),
    ("opd0_up_pad", 114),
    ("opd0_dn_pad", 118),
    ("opd0_lf_pad", 122),
    ("opd0_rt_pad", 126),
    ("res_op_x_str", 130),
    ("res_op_y_str", 134),
    ("tsk_lane_num", 198),
    ("res0_n", 214),
    ("res0_c", 226),
    ("res0_h", 242),
    ("res0_w", 258),
    ("opd0_n", 274),
    ("opd0_c", 286),
    ("opd0_h", 302),
    ("opd0_w", 318),
    ("opd1_n", 330),
    ("opd1_c", 342),
    ("opd1_h", 358),
    ("opd1_w", 374),
    ("res0_h_shift", 378),
    ("res0_w_shift", 382),
    ("opd0_h_shift", 386),
    ("opd0_w_shift", 390),
    ("opd1_h_shift", 394),
    ("opd1_w_shift", 398),
    ("res0_n_str", 417),
    ("res0_c_str", 436),
    ("opd0_n_str", 455),
    ("opd0_c_str", 474),
    ("opd1_n_str", 493),
    ("opd1_c_str", 512),
    ("opd2_n_str", 531),
    ("opd2_c_str", 550),
    ("opt_res_add_sign", 551),
    ("opd0_neq1", 552),
    ("opd1_neq1", 553),
    ("opt_opd3_const", 554),
    ("rsvd0", 576),
    ("res0_addr", 608),
    ("opd0_addr", 640),
    ("opd1_addr", 672),
    ("opd2_addr", 704),
    ("res0_h_str", 736),
    ("res0_w_str", 768),
    ("opd0_h_str", 800),
    ("opd0_w_str", 832),
    ("opd1_h_str", 864),
    ("opd1_w_str", 896),
    ("opd2_h_str", 928),
    ("opd2_w_str", 960),
    ("res1_addr", 992),
    ("opd3_addr", 1024),
)

dma_reg_def = (
    ("pio_gdma_enable", 1),
    ("des_type", 2),
    ("chain_end", 3),
    ("intr_en", 4),
    ("barrier_enable", 5),
    ("stride_enable", 6),
    ("direction", 8),
    ("acc_write_enable", 9),
    ("common_mode", 10),
    ("prefetch_disable", 11),
    ("hold_des_value", 12),
    ("reserved", 16),
    ("cmd_id", 32),
    ("special_func", 35),
    ("dst_data_format", 38),
    ("chw_copy", 39),
    ("sys_mem_type", 40),
    ("src_data_format", 43),
    ("lrn_shift_num", 47),
    ("lrn_shift_dir", 48),
    ("eng0_sync_id", 64),
    ("eng1_sync_id", 80),
    ("eng3_sync_id", 96),
    ("constant_value", 128),
    ("src_nstride", 160),
    ("src_cstride", 192),
    ("src_hstride", 224),
    ("src_wstride", 256),
    ("dst_nstride", 288),
    ("dst_cstride", 320),
    ("dst_hstride", 352),
    ("dst_wstride", 384),
    ("src_nsize", 400),
    ("src_csize", 416),
    ("src_hsize", 432),
    ("src_wsize", 448),
    ("dst_nsize", 464),
    ("dst_csize", 480),
    ("dst_hsize", 496),
    ("dst_wsize", 512),
    ("src_start_addr_l32", 544),
    ("dst_start_addr_l32", 576),
    ("src_start_addr_h8", 584),
    ("dst_start_addr_h8", 592),
    ("src_hshift", 616),
    ("src_wshift", 624),
    ("dst_hshift", 632),
    ("dst_wshift", 640),
    ("localmem_mask_l32", 672),
    ("localmem_mask_h32", 704),
    ("single_step", 705),
    ("debug_mode", 706),
)
